
polym-03:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004006b8 <_init>:
  4006b8:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4006bc:	910003fd 	mov	x29, sp
  4006c0:	9400003a 	bl	4007a8 <call_weak_fn>
  4006c4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4006c8:	d65f03c0 	ret

Disassembly of section .plt:

00000000004006d0 <.plt>:
  4006d0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4006d4:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0x10150>
  4006d8:	f947fe11 	ldr	x17, [x16, #4088]
  4006dc:	913fe210 	add	x16, x16, #0xff8
  4006e0:	d61f0220 	br	x17
  4006e4:	d503201f 	nop
  4006e8:	d503201f 	nop
  4006ec:	d503201f 	nop

00000000004006f0 <__libc_start_main@plt>:
  4006f0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4006f4:	f9400211 	ldr	x17, [x16]
  4006f8:	91000210 	add	x16, x16, #0x0
  4006fc:	d61f0220 	br	x17

0000000000400700 <__cxa_atexit@plt>:
  400700:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400704:	f9400611 	ldr	x17, [x16, #8]
  400708:	91002210 	add	x16, x16, #0x8
  40070c:	d61f0220 	br	x17

0000000000400710 <_ZNSt8ios_base4InitC1Ev@plt>:
  400710:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400714:	f9400a11 	ldr	x17, [x16, #16]
  400718:	91004210 	add	x16, x16, #0x10
  40071c:	d61f0220 	br	x17

0000000000400720 <abort@plt>:
  400720:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400724:	f9400e11 	ldr	x17, [x16, #24]
  400728:	91006210 	add	x16, x16, #0x18
  40072c:	d61f0220 	br	x17

0000000000400730 <__gmon_start__@plt>:
  400730:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400734:	f9401211 	ldr	x17, [x16, #32]
  400738:	91008210 	add	x16, x16, #0x20
  40073c:	d61f0220 	br	x17

0000000000400740 <printf@plt>:
  400740:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400744:	f9401611 	ldr	x17, [x16, #40]
  400748:	9100a210 	add	x16, x16, #0x28
  40074c:	d61f0220 	br	x17

0000000000400750 <_ZNSt8ios_base4InitD1Ev@plt>:
  400750:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400754:	f9401a11 	ldr	x17, [x16, #48]
  400758:	9100c210 	add	x16, x16, #0x30
  40075c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400760 <_start>:
  400760:	d280001d 	mov	x29, #0x0                   	// #0
  400764:	d280001e 	mov	x30, #0x0                   	// #0
  400768:	aa0003e5 	mov	x5, x0
  40076c:	f94003e1 	ldr	x1, [sp]
  400770:	910023e2 	add	x2, sp, #0x8
  400774:	910003e6 	mov	x6, sp
  400778:	580000c0 	ldr	x0, 400790 <_start+0x30>
  40077c:	580000e3 	ldr	x3, 400798 <_start+0x38>
  400780:	58000104 	ldr	x4, 4007a0 <_start+0x40>
  400784:	97ffffdb 	bl	4006f0 <__libc_start_main@plt>
  400788:	97ffffe6 	bl	400720 <abort@plt>
  40078c:	00000000 	.inst	0x00000000 ; undefined
  400790:	004008f0 	.word	0x004008f0
  400794:	00000000 	.word	0x00000000
  400798:	00400b20 	.word	0x00400b20
  40079c:	00000000 	.word	0x00000000
  4007a0:	00400ba0 	.word	0x00400ba0
  4007a4:	00000000 	.word	0x00000000

00000000004007a8 <call_weak_fn>:
  4007a8:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0x10150>
  4007ac:	f947f000 	ldr	x0, [x0, #4064]
  4007b0:	b4000040 	cbz	x0, 4007b8 <call_weak_fn+0x10>
  4007b4:	17ffffdf 	b	400730 <__gmon_start__@plt>
  4007b8:	d65f03c0 	ret
  4007bc:	00000000 	.inst	0x00000000 ; undefined

00000000004007c0 <deregister_tm_clones>:
  4007c0:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  4007c4:	91012000 	add	x0, x0, #0x48
  4007c8:	d0000081 	adrp	x1, 412000 <__libc_start_main@GLIBC_2.17>
  4007cc:	91012021 	add	x1, x1, #0x48
  4007d0:	eb00003f 	cmp	x1, x0
  4007d4:	540000a0 	b.eq	4007e8 <deregister_tm_clones+0x28>  // b.none
  4007d8:	90000001 	adrp	x1, 400000 <_init-0x6b8>
  4007dc:	f945e021 	ldr	x1, [x1, #3008]
  4007e0:	b4000041 	cbz	x1, 4007e8 <deregister_tm_clones+0x28>
  4007e4:	d61f0020 	br	x1
  4007e8:	d65f03c0 	ret
  4007ec:	d503201f 	nop

00000000004007f0 <register_tm_clones>:
  4007f0:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  4007f4:	91012000 	add	x0, x0, #0x48
  4007f8:	d0000081 	adrp	x1, 412000 <__libc_start_main@GLIBC_2.17>
  4007fc:	91012021 	add	x1, x1, #0x48
  400800:	cb000021 	sub	x1, x1, x0
  400804:	9343fc21 	asr	x1, x1, #3
  400808:	8b41fc21 	add	x1, x1, x1, lsr #63
  40080c:	9341fc21 	asr	x1, x1, #1
  400810:	b40000a1 	cbz	x1, 400824 <register_tm_clones+0x34>
  400814:	90000002 	adrp	x2, 400000 <_init-0x6b8>
  400818:	f945e442 	ldr	x2, [x2, #3016]
  40081c:	b4000042 	cbz	x2, 400824 <register_tm_clones+0x34>
  400820:	d61f0040 	br	x2
  400824:	d65f03c0 	ret

0000000000400828 <__do_global_dtors_aux>:
  400828:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40082c:	910003fd 	mov	x29, sp
  400830:	f9000bf3 	str	x19, [sp, #16]
  400834:	d0000093 	adrp	x19, 412000 <__libc_start_main@GLIBC_2.17>
  400838:	39412260 	ldrb	w0, [x19, #72]
  40083c:	35000080 	cbnz	w0, 40084c <__do_global_dtors_aux+0x24>
  400840:	97ffffe0 	bl	4007c0 <deregister_tm_clones>
  400844:	52800020 	mov	w0, #0x1                   	// #1
  400848:	39012260 	strb	w0, [x19, #72]
  40084c:	f9400bf3 	ldr	x19, [sp, #16]
  400850:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400854:	d65f03c0 	ret

0000000000400858 <frame_dummy>:
  400858:	17ffffe6 	b	4007f0 <register_tm_clones>

000000000040085c <_Z9TestBoundv>:
  40085c:	a9b97bfd 	stp	x29, x30, [sp, #-112]!
  400860:	910003fd 	mov	x29, sp
  400864:	910163a0 	add	x0, x29, #0x58
  400868:	94000049 	bl	40098c <_ZN4BaseC1Ev>
  40086c:	910103a0 	add	x0, x29, #0x40
  400870:	94000063 	bl	4009fc <_ZN4Sub1C1Ev>
  400874:	9100a3a0 	add	x0, x29, #0x28
  400878:	94000085 	bl	400a8c <_ZN4Sub2C1Ev>
  40087c:	910163a0 	add	x0, x29, #0x58
  400880:	f9000ba0 	str	x0, [x29, #16]
  400884:	910103a0 	add	x0, x29, #0x40
  400888:	f9000fa0 	str	x0, [x29, #24]
  40088c:	9100a3a0 	add	x0, x29, #0x28
  400890:	f90013a0 	str	x0, [x29, #32]
  400894:	b9006fbf 	str	wzr, [x29, #108]
  400898:	b9406fa0 	ldr	w0, [x29, #108]
  40089c:	7100081f 	cmp	w0, #0x2
  4008a0:	5400022c 	b.gt	4008e4 <_Z9TestBoundv+0x88>
  4008a4:	b9806fa0 	ldrsw	x0, [x29, #108]
  4008a8:	d37df000 	lsl	x0, x0, #3
  4008ac:	910043a1 	add	x1, x29, #0x10
  4008b0:	f8606822 	ldr	x2, [x1, x0]
  4008b4:	b9806fa0 	ldrsw	x0, [x29, #108]
  4008b8:	d37df000 	lsl	x0, x0, #3
  4008bc:	910043a1 	add	x1, x29, #0x10
  4008c0:	f8606820 	ldr	x0, [x1, x0]
  4008c4:	f9400000 	ldr	x0, [x0]
  4008c8:	f9400001 	ldr	x1, [x0]
  4008cc:	aa0203e0 	mov	x0, x2
  4008d0:	d63f0020 	blr	x1
  4008d4:	b9406fa0 	ldr	w0, [x29, #108]
  4008d8:	11000400 	add	w0, w0, #0x1
  4008dc:	b9006fa0 	str	w0, [x29, #108]
  4008e0:	17ffffee 	b	400898 <_Z9TestBoundv+0x3c>
  4008e4:	d503201f 	nop
  4008e8:	a8c77bfd 	ldp	x29, x30, [sp], #112
  4008ec:	d65f03c0 	ret

00000000004008f0 <main>:
  4008f0:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4008f4:	910003fd 	mov	x29, sp
  4008f8:	b9001fa0 	str	w0, [x29, #28]
  4008fc:	f9000ba1 	str	x1, [x29, #16]
  400900:	97ffffd7 	bl	40085c <_Z9TestBoundv>
  400904:	52800000 	mov	w0, #0x0                   	// #0
  400908:	a8c27bfd 	ldp	x29, x30, [sp], #32
  40090c:	d65f03c0 	ret

0000000000400910 <_Z41__static_initialization_and_destruction_0ii>:
  400910:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400914:	910003fd 	mov	x29, sp
  400918:	b9001fa0 	str	w0, [x29, #28]
  40091c:	b9001ba1 	str	w1, [x29, #24]
  400920:	b9401fa0 	ldr	w0, [x29, #28]
  400924:	7100041f 	cmp	w0, #0x1
  400928:	540001e1 	b.ne	400964 <_Z41__static_initialization_and_destruction_0ii+0x54>  // b.any
  40092c:	b9401ba1 	ldr	w1, [x29, #24]
  400930:	529fffe0 	mov	w0, #0xffff                	// #65535
  400934:	6b00003f 	cmp	w1, w0
  400938:	54000161 	b.ne	400964 <_Z41__static_initialization_and_destruction_0ii+0x54>  // b.any
  40093c:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  400940:	91014000 	add	x0, x0, #0x50
  400944:	97ffff73 	bl	400710 <_ZNSt8ios_base4InitC1Ev@plt>
  400948:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  40094c:	91010002 	add	x2, x0, #0x40
  400950:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  400954:	91014001 	add	x1, x0, #0x50
  400958:	90000000 	adrp	x0, 400000 <_init-0x6b8>
  40095c:	911d4000 	add	x0, x0, #0x750
  400960:	97ffff68 	bl	400700 <__cxa_atexit@plt>
  400964:	d503201f 	nop
  400968:	a8c27bfd 	ldp	x29, x30, [sp], #32
  40096c:	d65f03c0 	ret

0000000000400970 <_GLOBAL__sub_I__Z9TestBoundv>:
  400970:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400974:	910003fd 	mov	x29, sp
  400978:	529fffe1 	mov	w1, #0xffff                	// #65535
  40097c:	52800020 	mov	w0, #0x1                   	// #1
  400980:	97ffffe4 	bl	400910 <_Z41__static_initialization_and_destruction_0ii>
  400984:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400988:	d65f03c0 	ret

000000000040098c <_ZN4BaseC1Ev>:
  40098c:	d10043ff 	sub	sp, sp, #0x10
  400990:	f90007e0 	str	x0, [sp, #8]
  400994:	90000000 	adrp	x0, 400000 <_init-0x6b8>
  400998:	91316001 	add	x1, x0, #0xc58
  40099c:	f94007e0 	ldr	x0, [sp, #8]
  4009a0:	f9000001 	str	x1, [x0]
  4009a4:	f94007e0 	ldr	x0, [sp, #8]
  4009a8:	52800021 	mov	w1, #0x1                   	// #1
  4009ac:	b9000801 	str	w1, [x0, #8]
  4009b0:	f94007e0 	ldr	x0, [sp, #8]
  4009b4:	52800041 	mov	w1, #0x2                   	// #2
  4009b8:	b9000c01 	str	w1, [x0, #12]
  4009bc:	d503201f 	nop
  4009c0:	910043ff 	add	sp, sp, #0x10
  4009c4:	d65f03c0 	ret

00000000004009c8 <_ZN4Base5printEv>:
  4009c8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4009cc:	910003fd 	mov	x29, sp
  4009d0:	f9000fa0 	str	x0, [x29, #24]
  4009d4:	f9400fa0 	ldr	x0, [x29, #24]
  4009d8:	b9400801 	ldr	w1, [x0, #8]
  4009dc:	f9400fa0 	ldr	x0, [x29, #24]
  4009e0:	b9400c02 	ldr	w2, [x0, #12]
  4009e4:	90000000 	adrp	x0, 400000 <_init-0x6b8>
  4009e8:	912f6000 	add	x0, x0, #0xbd8
  4009ec:	97ffff55 	bl	400740 <printf@plt>
  4009f0:	d503201f 	nop
  4009f4:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4009f8:	d65f03c0 	ret

00000000004009fc <_ZN4Sub1C1Ev>:
  4009fc:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400a00:	910003fd 	mov	x29, sp
  400a04:	f9000fa0 	str	x0, [x29, #24]
  400a08:	f9400fa0 	ldr	x0, [x29, #24]
  400a0c:	97ffffe0 	bl	40098c <_ZN4BaseC1Ev>
  400a10:	90000000 	adrp	x0, 400000 <_init-0x6b8>
  400a14:	91310001 	add	x1, x0, #0xc40
  400a18:	f9400fa0 	ldr	x0, [x29, #24]
  400a1c:	f9000001 	str	x1, [x0]
  400a20:	f9400fa0 	ldr	x0, [x29, #24]
  400a24:	52800081 	mov	w1, #0x4                   	// #4
  400a28:	b9000801 	str	w1, [x0, #8]
  400a2c:	f9400fa0 	ldr	x0, [x29, #24]
  400a30:	528000a1 	mov	w1, #0x5                   	// #5
  400a34:	b9000c01 	str	w1, [x0, #12]
  400a38:	f9400fa0 	ldr	x0, [x29, #24]
  400a3c:	528000c1 	mov	w1, #0x6                   	// #6
  400a40:	b9001001 	str	w1, [x0, #16]
  400a44:	d503201f 	nop
  400a48:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400a4c:	d65f03c0 	ret

0000000000400a50 <_ZN4Sub15printEv>:
  400a50:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400a54:	910003fd 	mov	x29, sp
  400a58:	f9000fa0 	str	x0, [x29, #24]
  400a5c:	f9400fa0 	ldr	x0, [x29, #24]
  400a60:	b9400801 	ldr	w1, [x0, #8]
  400a64:	f9400fa0 	ldr	x0, [x29, #24]
  400a68:	b9400c02 	ldr	w2, [x0, #12]
  400a6c:	f9400fa0 	ldr	x0, [x29, #24]
  400a70:	b9401003 	ldr	w3, [x0, #16]
  400a74:	90000000 	adrp	x0, 400000 <_init-0x6b8>
  400a78:	912fa000 	add	x0, x0, #0xbe8
  400a7c:	97ffff31 	bl	400740 <printf@plt>
  400a80:	d503201f 	nop
  400a84:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400a88:	d65f03c0 	ret

0000000000400a8c <_ZN4Sub2C1Ev>:
  400a8c:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400a90:	910003fd 	mov	x29, sp
  400a94:	f9000fa0 	str	x0, [x29, #24]
  400a98:	f9400fa0 	ldr	x0, [x29, #24]
  400a9c:	97ffffbc 	bl	40098c <_ZN4BaseC1Ev>
  400aa0:	90000000 	adrp	x0, 400000 <_init-0x6b8>
  400aa4:	9130a001 	add	x1, x0, #0xc28
  400aa8:	f9400fa0 	ldr	x0, [x29, #24]
  400aac:	f9000001 	str	x1, [x0]
  400ab0:	f9400fa0 	ldr	x0, [x29, #24]
  400ab4:	528000e1 	mov	w1, #0x7                   	// #7
  400ab8:	b9000801 	str	w1, [x0, #8]
  400abc:	f9400fa0 	ldr	x0, [x29, #24]
  400ac0:	52800101 	mov	w1, #0x8                   	// #8
  400ac4:	b9000c01 	str	w1, [x0, #12]
  400ac8:	f9400fa0 	ldr	x0, [x29, #24]
  400acc:	52800121 	mov	w1, #0x9                   	// #9
  400ad0:	b9001001 	str	w1, [x0, #16]
  400ad4:	d503201f 	nop
  400ad8:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400adc:	d65f03c0 	ret

0000000000400ae0 <_ZN4Sub25printEv>:
  400ae0:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400ae4:	910003fd 	mov	x29, sp
  400ae8:	f9000fa0 	str	x0, [x29, #24]
  400aec:	f9400fa0 	ldr	x0, [x29, #24]
  400af0:	b9400801 	ldr	w1, [x0, #8]
  400af4:	f9400fa0 	ldr	x0, [x29, #24]
  400af8:	b9400c02 	ldr	w2, [x0, #12]
  400afc:	f9400fa0 	ldr	x0, [x29, #24]
  400b00:	b9401003 	ldr	w3, [x0, #16]
  400b04:	90000000 	adrp	x0, 400000 <_init-0x6b8>
  400b08:	91300000 	add	x0, x0, #0xc00
  400b0c:	97ffff0d 	bl	400740 <printf@plt>
  400b10:	d503201f 	nop
  400b14:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400b18:	d65f03c0 	ret
  400b1c:	00000000 	.inst	0x00000000 ; undefined

0000000000400b20 <__libc_csu_init>:
  400b20:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400b24:	910003fd 	mov	x29, sp
  400b28:	a901d7f4 	stp	x20, x21, [sp, #24]
  400b2c:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0x10150>
  400b30:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0x10150>
  400b34:	91340294 	add	x20, x20, #0xd00
  400b38:	9133c2b5 	add	x21, x21, #0xcf0
  400b3c:	a902dff6 	stp	x22, x23, [sp, #40]
  400b40:	cb150294 	sub	x20, x20, x21
  400b44:	f9001ff8 	str	x24, [sp, #56]
  400b48:	2a0003f6 	mov	w22, w0
  400b4c:	aa0103f7 	mov	x23, x1
  400b50:	9343fe94 	asr	x20, x20, #3
  400b54:	aa0203f8 	mov	x24, x2
  400b58:	97fffed8 	bl	4006b8 <_init>
  400b5c:	b4000194 	cbz	x20, 400b8c <__libc_csu_init+0x6c>
  400b60:	f9000bb3 	str	x19, [x29, #16]
  400b64:	d2800013 	mov	x19, #0x0                   	// #0
  400b68:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400b6c:	aa1803e2 	mov	x2, x24
  400b70:	aa1703e1 	mov	x1, x23
  400b74:	2a1603e0 	mov	w0, w22
  400b78:	91000673 	add	x19, x19, #0x1
  400b7c:	d63f0060 	blr	x3
  400b80:	eb13029f 	cmp	x20, x19
  400b84:	54ffff21 	b.ne	400b68 <__libc_csu_init+0x48>  // b.any
  400b88:	f9400bb3 	ldr	x19, [x29, #16]
  400b8c:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400b90:	a942dff6 	ldp	x22, x23, [sp, #40]
  400b94:	f9401ff8 	ldr	x24, [sp, #56]
  400b98:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400b9c:	d65f03c0 	ret

0000000000400ba0 <__libc_csu_fini>:
  400ba0:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400ba4 <_fini>:
  400ba4:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400ba8:	910003fd 	mov	x29, sp
  400bac:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400bb0:	d65f03c0 	ret
